The present invention relates to caching the memory of a computer system and, in particular, to a cache with a temporal-spatial organization.
Many legacy architectures, such as S/390, permit the program to be self-modifying, meaning that a program may store into its own code, thus altering itself dynamically. This behavior is referred to as Storing To the Instruction Stream (STIS). Even architectures that do not directly facilitate dynamic code self-modification must still provide a means for flushing cached instructions whenever new code is loaded into memory, to maintain instruction cache coherency.
While methods do exist for handling STIS in the straightforward single-address-space single-processor case, the present invention addresses the additional complexity when multiple virtual address spaces and/or processors are involved. One such method for handling STIS in a single-processor case is described in U.S. patent application Ser. No. 09/992,130, filed on Nov. 14, 2001, and titled, “Processing of Self-Modifying Code under Emulation.” The disclosure of this application, published on May 15, 2003 as Published Application No. 20030093775 is herein incorporated by reference.